In the prior art, there is the electronic component built-in package in which a semiconductor chip is mounted between stacked wiring substrates in a state that the semiconductor chip is buried in a sealing resin. In such electronic component built-in package, the semiconductor chip is mounted on a lower wiring substrate, and then solder bumps of an upper wiring substrate are connected to the lower wiring substrate such that the semiconductor chip is housed between them.
Subsequently, a sealing resin is filled in a space between the lower wiring substrate and the upper wiring substrate, and thus the semiconductor chip is sealed with the sealing resin.
In this electronic component built-in package, the sealing resin is filled in the linked space between the lower wiring substrate and the upper wiring substrate. Therefore, the sealing resin is formed in the whole area on the lower wiring substrate. As a result, it cannot be simply implemented to form an exposed area on which the sealing resin is not formed on a part of the lower wiring substrate.
A related art is disclosed in International Publication Pamphlet No. WO2007-069606.